1. Field of the Invention
The present invention relates generally the design of analog to digital converters (ADC), and more specifically to a method and apparatus for reducing the time to convert an analog input sample to a digital code in an ADC.
2. Related Art
An ADC refers to a component which receives an analog sample as input and provides (generates) a digital code corresponding to strength of the analog signal at various time instances (samples) as output. In an embodiment, the digital code equals (Vi*2n/Vref), wherein Vi represents the voltage of the input (analog) sample, Vref the reference voltage, * and / representing the multiplication and division operations respectively.
There is a general need to reduce the time to convert analog samples to corresponding digital codes. By reducing such time, the overall speed (and thus the throughput performance) of operation of systems/devices incorporating ADCs, can be advantageously enhanced. One reason for the low speed of ADCs is illustrated below with examples.
FIG. 1 is a block diagram of a pipe line ADC in one embodiment. ADC 100 is shown containing sample and hold amplifier (SHA) 110, stages 120-1 through 120-S, and digital error correction block 130. Each block is described below in further detail.
SHA 110 samples the input analog signal received on path 101, and holds the voltage level of the sample on path 111 for further processing by stage 120-1. Digital error correction block 130 receives sub-codes from various stages (on paths 123-1 through 123-S respectively), and generates a digital code corresponding to the sample received on path 101. Various error correction approaches, well known in the relevant arts, may be used to correct any errors in the received sub-codes. The generated digital code is provided on path 139 as a final digital code corresponding to the voltage of a sample on the input analog signal at a particular time instant.
Each stage 120-1 through 120-S generates a sub-code (based on the reference signal Vref received on path 152) corresponding to a voltage level of an analog signal received as an input, and an amplified residue signal as an input to a (any) next stage. For example, stage 120-1 converts a voltage level on path 111 to generate a sub-code on path 123-1, and the amplified residue signal generated on path 112 is provided as an input to stage 120-2. A common reference signal Vref is provided to stages 120-1 through 120-S. FIG. 2 further illustrates (logical) components contained in each stage (described with reference to stage 120-1 only, for conciseness) of a pipe line ADC according to a known approach.
FIG. 2 depicts the details of SHA 110 and stage 120-1 in one embodiment. As shown there, SHA 110 contains sampling circuit 210 and SHA amplifier 220, and stage 120-1 contains DAC-subtractor circuit 240, flash-ADC 260 (an example implementation of a quantizer), and gain amplifier 280. Each component is described briefly below.
Sampling circuit 210 samples the signal received on path 101, and provides the samples to SHA amplifier 220 at specific time points (determined by a time clock, not shown). Sampling circuit 210 is often implemented using capacitors and switches, as is well known in the relevant arts. SHA amplifier 220 amplifies the samples received from sampling circuit 210, and holds the amplified values for a time duration based on the requirements (timing/accuracy requirements) of stage 120-1.
Flash ADC 260 generates a sub-code representing the voltage level of the input sample received on path 111, and the sub-code is provided to on path 123-1 to DAC-subtractor circuit 240 as well as digital error correction block 130. DAC-subtractor circuit 240 receives the input sample on path 111 and Vref on path 152, and generates a residue signal having a voltage level of (Vi−(digital-code*Vref/2n)), wherein n represents the number of bits in each sub-code, and (digital-code*Vref/2n) represents a voltage equivalent of the sub-code. Gain amplifier 280 amplifies the residue signal, and provides the amplified residue signal for processing in stages downstream.
Aspects of the present invention provide advantages such as increased throughput performance. The features can be appreciated by understanding the details of prior embodiments, which do not implement one or more of such features. Accordingly, the prior embodiments are described below with reference to FIGS. 3 and 4.
FIG. 3 depicts the further details of stage 120-1 in one embodiment assuming a 1-bit digital code is generated for simplicity. Flash ADC 260 is shown containing capacitor 310 and comparator 320, and switched capacitor amplifier 340 (which performs sampling of the input signal, subtracts the voltage equivalent of the digital code, and amplifies the result of subtraction, and thus containing both DAC-subtractor circuit 240 and gain amplifier 280) is shown containing capacitors 370 and 380, switches 360A-360C and 385, and operational amplifier (op-amp) 390. The components are described below in further detail.
First it is noted that, in order to avoid obscuring the features of the present invention, the description henceforth is provided with reference to single ended implementations. The extension of the approaches to differential circuits will be apparent to one skilled in the relevant arts by reading the disclosure provided herein, and such implementations are contemplated to be covered by various aspects of the present invention.
Capacitor 310 represents the input capacitance of flash-ADC 260. Capacitor 310 charges to the input sample voltage on path 111 when switch 315 is closed. Switch 315 is open after a pre-determined time duration intended to allow the capacitor to complete charging (in sampling phase, overlapping with the hold phase of SHA 110). Comparator 320 is then enabled to provide a comparison result of capacitor voltage (on 310) with Vref/2, as shown.
Capacitor 370 samples the input sample voltage on path 111 when switch 360A is closed. Switch 360A is opened after a pre-determined time duration intended to allow the capacitor to complete charging (in sampling phase). Switches 385, 360B and 360C are kept open during sampling phase. Once capacitor 370 is charged, switch 360A is opened and switch 385 is closed during the hold phase.
Only one switches 360B (to subtract Vref) and 360C (to subtract common mode reference, or ground in case of single ended operation) is closed based on the result of the output of flash-ADC 260, to achieve any needed subtraction. The difference of the sampled input voltage (during sampling phase) and Vref/CM is transferred to feedback capacitor 380. Op-amp 390 amplifies the difference (residue) based on ratio of the capacitance of capacitors 380 and 370. The amplified residue signal is provided to the next stage 112.
While the embodiments of above provide the desired digital value corresponding to a sampled input voltage, there may be several disadvantages with the related approach. For example, SHA amplifier 220 may need to be implemented to support two components of loads, i.e., from flash ADC 260 and DAC subtractor circuit 240. SHA amplifier 220 needs to be implemented with a high accuracy, consistent with the requirements of DAC-substractor 240, even though flash ADC may tolerate lesser accuracy. Driving such high load as well as providing a high accuracy, often presents design challenges and may be undesirable at least in some environments.
Another disadvantage with such a system is low throughput performance, as described below with respect to the timing diagram of FIG. 4. Signals 401 and 402 respectively represent the sampling and hold phases in SHA 110. Signals 420, 430 and 460 respectively represent the operation of switches 315, 360A, and 360B/360C. Signal 440 represents the duration in which flash-ADC 260 determines the sub-code. The timing relationship between these signals is described below in detail.
Input signal 101 is sampled (by SHA 110) between time points 411 and 412. SHA amplifier 220 holds the sampled and amplified signal on path 111 between time points 413 (following immediately after time point 412) and 414. Switches 315 and 360A are closed between time point 413 and 414, causing capacitors 310 and 370 to store charge proportionate to sampled input voltage. Thus, time duration between 413 and 414 represents the sampling duration of both flash ADC 260 and DAC-subtractor circuit 240.
Flash ADC 260 generates the sub-code by comparing the relevant signals in time duration 441-442. Time point 441 may start after time point 414 since earlier opening of switch 315 causes noise at the input of capacitor 370 (which is undesirable at least to the high precision requirements for DAC-subtractor circuit 240 in the signal path). Thus, sub-code value corresponding to the sampled value at time point 414 is available after time point 442 for use by DAC-subtractor circuit 240.
Thus, switches 360B or 360C can be closed after time point 442. Accordingly, the desired amplification is shown occurring between time points 462 (following 442) and 463. The amplified residue signal is made available to the next stage 120-2 following time point 463. Hence, the total processing time consumed by stage 120-1 is duration 413-463, which may approximately equals the sum of sampling phase duration 413-414, sub-code generation duration 441-442, and DAC-subtractor hold time 462-463.
As noted above, it is often desirable to provide ADCs of high throughput performance and thus it may be desirable to reduce the processing time of each ADC stage. Accordingly, what is needed is a ADC architecture which meets one or more of the requirements noted above.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit (s) in the corresponding reference number.